As is known, phase-change memories are new-generation non-volatile memories in which, in order to store information, characteristics of materials having the property of switching between phases with different electrical characteristics are exploited. These materials may switch between a disorderly/amorphous phase and a crystalline or polycrystalline orderly phase; different phases are characterized by different values of resistivity and consequently are associated to different values of a stored data item. For example, the elements of Group VI of the Periodic Table, such as tellurium (Te), selenium (Se), or antimony (Sb), also known as chalcogenides or chalcogenic materials, may be used for manufacturing phase-change memory cells. In particular, an alloy formed by germanium (Ge), antimony (Sb), and tellurium (Te), known as GST (having the chemical composition Ge2Sb2Te5), is currently widely used in these memory cells.
Phase changes may be obtained by increasing locally the temperature of the cells of chalcogenic material, through resistive electrodes (known in general as heaters) arranged in contact with corresponding regions of chalcogenic material.
Access (or selection) devices (for example, MOSFETs) are connected to the heaters and selectively enable passage of an electric programming current through them. This electric current, by the Joule effect, generates the temperatures required for phase change.
In particular, when the chalcogenic material is in the amorphous state, and thus has a high resistivity (the so-called RESET state), it is necessary to apply a current/voltage pulse (or a suitable number of current/voltage pulses) of a duration and amplitude such as to enable the chalcogenic material to cool down slowly. Subjected to this treatment, the chalcogenic material changes its state and switches from the high-resistivity state to a low-resistivity state (the so-called SET state). Conversely, when the chalcogenic material is in the SET state, it is necessary to apply a current/voltage pulse having an appropriate duration and a high amplitude, so as to cause the chalcogenic material to return into the high-resistivity amorphous RESET state.
During reading, the state of the chalcogenic material is detected by applying a voltage sufficiently low as not to cause sensible heating thereof, and by then reading the value of the current that flows in the memory cell through a sense amplifier. Given that the current is proportional to the conductivity of the chalcogenic material, it is possible to determine in which state the material is set, and consequently to determine the data item stored in the memory cell.
FIG. 1 shows a PCM device 1, which comprises a memory array 2 formed by a plurality of memory cells 3, arranged in rows, or word lines, and columns, or bit lines. Purely by way of example, the memory array 2 shown in FIG. 1 has three word lines, designated by WL, and three bit lines, designated by BL, which enable addressing of nine memory cells 3.
Each memory cell 3 is formed by a storage element 4a and by an access element 4b, which are connected in series between a respective bit line BL and a terminal at a reference potential (for example, ground).
The storage element 4a includes an element of phase-change material (for example, a calchogenide, such as GST) and consequently is able to store data in the form of levels of resistance associated to the different phases assumed by the material itself.
The access element 4b is formed by an N-channel MOSFET, the drain terminal of which is connected to a first terminal of the storage element 4a, the second terminal of which is connected to a corresponding bit line BL. The source terminal of the MOSFET is connected to ground, whereas the gate terminal is connected to a corresponding word line WL. In this regard, a word line WL is defined by the set of the gate terminals of the access elements 4b aligned along a same row; instead, a bit line BL is defined by the set of the second terminals of the storage elements 4a aligned along a same column.
In practice, given a memory cell 3, the second terminal of the storage element 4a and the gate terminal of the access element 4b form, respectively, a bit-line terminal and a word-line terminal of the memory cell 3.
The PCM device 1 further comprises a column decoder 8 and a row decoder 10, which enable selection of the memory cells 3, on the basis of address signals received at input (designated as a whole by AS). The address signals AS may be generated by a control logic 11, which further controls the column decoder 8 and the row decoder 10 so as to enable reading and writing (also known as programming) of the memory cells 3 addressed by the address signals AS. Albeit not shown, the control logic 11 supplies to the column decoder 8 and to the row decoder 10 also control signals in order to control the aforementioned read/write operations.
The column decoder 8 and the row decoder 10 enable biasing, and thus selection, of the word lines WL and of the bit lines BL each time addressed so as to select the memory cells 3 connected thereto. In this way, reading and writing of the memory cells 3 are enabled.
In greater detail, the row decoder 10 is designed to select, on the basis of the address signals AS, a corresponding word line WL. The other word lines WL are deselected. For this purpose, the row decoder 10 comprises a decoding stage 12 and a plurality of driving circuits 14.
The decoding stage 12 receives the address signals AS and controls the driving circuits 14 on the basis of the address signals AS. Each driving circuit 14 then has an input, which is connected to the decoding stage 12. Each driving circuit 14 further has an output, which is connected to a corresponding word line WL. In addition, each driving circuit 14 is formed by a corresponding number of MOSFETs (not visible in FIG. 1). For example, each driving circuit 14 may be formed by a corresponding inverter circuit.
In practice, the driving circuit 14 biases, and thus controls, the gate terminals of the access elements 4b connected to the corresponding word line WL so as to select/deselect the word line WL, on the basis the address signals AS.
As regards the column decoder 8, it should be noted that the operations of programming of the SET and RESET states may be carried out on “words” containing a number Nb of bits (Nb being an integer higher than or equal to 1), i.e., on a number Nb of memory cells 3 connected to a same word line WL. The column decoder 8 is consequently designed to select simultaneously, on the basis of the address signals AS, a set of Nb bit lines BL, which will also be referred to as “set of bit lines to be programmed”.
In practice, the column decoder 8 co-operates with the row decoder 10 so that, during the steps of reading or programming of any memory cell 3 selected, through the storage element 4a of this memory cell 3 a read current or a programming current, respectively, flows. For this purpose, the column decoder 8 is configured to provide internally two distinct paths towards the bit lines BL of the memory array 2 each time selected: a reading path, which during the reading step electrically connects each bit line BL selected to a sense-amplifier stage 17; and a programming path, which during the programming step electrically connects each bit line BL selected to a writing stage 18.
The sense-amplifier stage 17 is configured to compare the read current that circulates in the memory cell 3 selected with a reference current in order to determine the data item stored in the memory cell 3 selected. The writing stage 18 is configured to supply the programming current, which in turn depends upon whether a SET state or a RESET state is programmed in the memory cell 3 selected.
As regards programming of the memory cells 3, it should be noted that, during the writing operations, it is necessary to supply to the storage elements 4a current pulses of a high value, both in the case of programming of the SET state and in the case of programming of the RESET state.
For example, programming of the SET state may be obtained through a trapezial current pulse having an amplitude, for example, comprised between 100 μA and 200 μA, whereas programming of the RESET state may be obtained through a rectangular current pulse having a higher amplitude, for example, between 200 μA and 700 μA.
As regards, instead, the read current, it has values (for example, 30 PA) lower than the write current, so as not to damage the state programmed.
This being said, PCM devices afford numerous advantages, amongst which a high scalability. However, on account of the high programming currents, the MOSFETs that form the driving circuits 14 must be able to withstand voltages that are not particularly low (for example, 1.8 V). For this purpose, these MOSFETs may be manufactured with the so-called 150-nm technology; however, the driving circuits 14 thus manufactured are relatively slow.
In practice, the aforementioned driving circuits 14 are optimized for carrying out the programming operations, which envisage that selection of the word lines WL may occur in not particularly short times (for example, longer than 50 ns) and entail generation of relatively high voltages. However, in some contexts of application (for example, in the automotive sector), there is felt the need to be able to select the word lines WL in a fast way (for example, in times shorter than 3 ns) during the reading step. This result appears to be problematical to obtain with just the use of the aforementioned MOSFETs, without incurring in a considerable increase in the area occupation, and thus in the costs.